Logic Designers Handbook. Circuits and Systems
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Electromagnetic Compossibility, Heinz M. Schlicke Gottling Taylor Multivariable Control: An Introduction, P. Sinha Edstrom, Jr. Greenway, and William P. Kelly Browne, Jr. Kit Sum Hurst Emery Mahmoud, Mohamed F. Hassan, and Mohamed G. Darwish Fathi and Cedric V. Armstrong Sponsored by Ontario Centre for Microelectronics Perry Tzafestas Buchanan Dexter Miniet Fuqua Kussy and Jack L.
Warren Salmon Protective Relaying: Principles and Applications, J.
Lewis Blackburn Powell Chalam Hnatek Swartzlander, Jr. Levinson Alford Kheir Rigling This means that in a decoding situation, the only active decoder output is ground in either definition of logic levels. The circuit design is such that a number of gates may be connected together at a common point to produce a positive OR function. In Figure 19, if either gate output goes to ground, the output of the logic will be ground.
Thus a convenient function is derived. If the DCD gate could be used as a separate logic element not in conjunction with pulse amplifiers or flip-flops its positive and negative definitions would be as shown in Figure People, on the other hand, are more accustomed to decimal numbers, and for this reason it is often desirable to build a computing system which can be operated in decimal. To build a decimal computer with two-state devices, it is necessary to encode the decimal digits with binary bits. Four binary bits are needed. Although only 10 of the 16 permutations possible with the 4-bit decade will be used, all are available.
Desirable features of the code are: ease in performing arithmetic operation, economy of storage space, economy of gating opera- tions, error detection and correction, and simplicity. Several possible codes are shown below, followed by a detailed explanation of arithmetic operations using two especially convenient codes, the 8 4 2 1 and the Excess 3.
Arithmetic operations are easily performed using the same basic method as in binary since the number sequence is the same. The Excess 3 code is not a weighted code, but since it follows the same number sequence as binary, it is useful in arithmetic operations. Addition is facilitated since the need for a correction factor is easily detected and easily imple- mented. Because it is self-complementing, the Excess 3 code is also useful in subtraction. The 2 4 2 1 is a self-complementing weighted code which is commonly employed in counting systems.
Other examples of four-bit weighted codes include the 5 4 2 1, the 5 3 11, and the 7 code. All of these codes are shown in Figure More than four bits may be used in each decade to provide additional special features such as the detection of errors and the simplification of decoding. However, in binary notation sitxeen states are represented with four bits. In binary-coded decimal only ten of these states are used; therefore, special correction factors must be added to account for the six unused states. Counting In a binary-coded decimal BCD counter, the corrective action is very simple.
The counter is divided into four-bit decades, and special gating is added to each decade. This gating detects the number 9 and reroutes the next count pulse so that it will reset the decade to and generate a carry to the next decade. In a down counter, the same approach is used.
Starting with a standard binary down counter, the number is detected, and the next count input resets the counter to the appropriate 9 designation and produces a borrow. A reversible BCD counter may be implemented by combining the techniques for the individual up and down counters. Such a counter, however, is more difficult to construct than a single direction counter since provision must be made for isolating the carry and borrow chains and for assuring that count up and count down signals do not occur simultaneously.
When addition is to be performed in a decade by decade fashion serial addition with parallel decades , either code is useful. If addition is performed in parallel, however, the Excess 3 code is superior to the 8 4 2 1 code. In 8 4 2 1 code the sum will be correct if it does not exceed 9. Addition of 8 4 2 1 coded numbers has the disadvantage that a carry signal can be generated during the correction process. For this reason each decade in the adder has to be corrected individually. Therefore it is not a desirable code in a parallel adder see Figure An initial carry requires a positive correction; no carry, a negative correction.
The correction process will never yield an additional carry, thus simultaneous correction of all decades is possible. The steps for performing Excess 3 addition are: 1. Add the two BCD numbers in binary fashion 2. Check each decade for a carry signal Subtract 3 from each decade in which a carry has not occurred, while simultaneously adding 3 to each decade in which the carry signal has occurred. Subtracting 3 from a decade is done by adding and using the end around carry from the most significant bit of the decade.
This is a method of 9's complement subtraction, described under subtraction below. Figure 24 Addition with the Excess 3 code Subtraction Since subtraction is the inverse of addition, the same circuits may be used for both operations. Subtractions by this process is known as the system of adding complements. The 9's complement of any number is that number which is obtained by subtracting each individual digit from 9. With a self-complementing BCD code, such as Excess 3, the 9's complement of any number can be easily obtained by changing all zeros to ones and all ones to zeros.
Figure 25 illustrates Excess 3 code with 9's complement notation. During the first step of the addition process the individual bits in the decimal decades and in the sign bits are added just as in binary. Carries propagate from each digit to the digit of more significance and from the most significant digit to the sign bit. If the sign bit produces a carry, it is added to the least significant decade, a process known as end around carry. Figure 26 Subtraction with the Excess 3 code, 9's complement notation 20 After this initial portion of the subtraction, a correction factor must be applied just as in addition.
That is, a binary 3 must be added to each decade in which a carry signal has occurred, and binary 3 must be subtracted from each decade in which a carry signal did not occur. Subtraction of the correction factor may be performed in the same way as well as the overall subtraction. However, the subtraction in this case operates only on the individual digits. Thus, if a carry occurs from the most significant bit of the digit, it is not carried out to the next digit; rather, it is added into the least significant bit of the same digit.
A second method of performing subtraction is through the use of the 10's complement notation. The 10's complement of any number may be obtained by adding 1 to the 9's complement. Operations are similar to those used in the 9's complement notation except that the end around carry is not required. Hence this is useful in systems where a feed back loop would be particularly time consuming. The biquinary code is commonly used when error detection is required. It is a 7-bit weighted code in which two ones and five zeros appear in the representation of any number; thus it is always possible to detect single errors, and it is often possible to detect multiple errors.
The ten-bit weighted code shown in Figure 27 allows any number to be represented with a single 1 and nine zeros. This code is often used in counting operations; the counter is a ten-stage shift register with the final stage connected to the initial stage. This counter, often given the name of ring counter, requires no carrying propagate time and the numbers may be decoded into ten lines without additional gates. The switch-tail ring counter is a five-stage ring counter with reversed feed-back from the initial stage to the final stage. It requires fewer flip-flops than the ring counter and has the same advantage that no carry propagate time is required.
Any state may be decoded by a two-input gate conditioned by two neighboring flip-flops. The diode gate is used in the R 2-mega hertz series to combine, amplify, invert, and standardize the signals which represent various logic functions.
Logic synthesis - Wikipedia
Figure 1 is a schematic of a simple diode gate with one input. As a result, the PNP transistor is turned on, forming a short circuit between the collector and the emitter. Thus, when the input voltage is negative, the output voltage is ground. Since the output is from a saturated transistor, it has a low output impedance and good driving power. When the diode gate input voltage is ground, the biasing diodes and the resistor, which is connected to the lOv supply, hold the transistor base more positive than the emitter, and the transistor is turned off.
The output is then an open circuit, and it will follow the voltage of any other circuit connected to it. When the tran- sistor is on, the diode is cut off and the load resistor follows the output to ground. The single-input diode gate therefore has three functions. First, it inverts the input signal. Second, it standardizes the output voltage to — 3v or ground if the clamped load diode and resistor are connected. Third, since the output current available from the transistor is much greater than the required input current, the diode gate amplifies.
A fourth function, gating, is obtained by adding more diode inputs to the node point, as shown in Figure 2. Thus, when any input terminal is grounded, the node terminal is also at ground and the circuit output is at — 3v. If all of the inputs are negative, the node terminal will be negative and the circuit output will be at ground. Gating functions may also be performed by wiring together two or more diode gate outputs and one load resistor, as shown in Figure 3.
When any input is negative, it saturates the corresponding transistor and forces the output line to ground. If all inputs are at ground, all of the transistors are open circuits and the output voltage, determined by the clamped load resistor, is — 3v. A drawing that showed all of the circuit components, however, would be tedious to draw and difficult to read.
For this reason, the diagrams that follow use a shorthand notation which represents one or more components as a single functional unit.
Digital Logic Circuit Analysis and Design, Victor P. Nelson
Referring to Figure 4, diodes are shown in the conventional way. The transistor circuit, including the, biasing resistors and diodes, is shown as a simple rectangle with an arrowhead indicating the direction of the transistor emitter. This part of the circuit is called an inverter because of the function it performs. The load resistor is shown as a resistor with a large dot at the top indicating that it is diode clamped to — 3v. With these sym- bols, one can easily and quickly draw complex logical functions.
A solid diamond indicates a — 3v level, and an open diamond indicates a ground level. In the 2-input diode gate of Figure 5, for example, if input A and input B are both negative, the output will be at ground. If either A or B is at ground, the output will be negative. It provides logical isolation between pulse and level inputs and produces a logical delay which is essential for sampling flip-flops at the same time they are being changed.
It also acts as a logical AND gate since both pulse and level inputs must meet certain requirements for a signal to appear at the output. Either positive pulses or positive-going level changes both — 3v to ground may be used as the pulse input.
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If the level input is held at ground and the pulse input is held at — 3v, the capacitor will become charged after the setup time has passed. If the pulse input then suddenly goes to ground, a positive-going pulse will appear at the output. There is delay at the level input, but the pulse input goes to the output without delay.
Even if the level input changes simultaneously with a positive transition at the pulse input, the delay acts as a temporary memory: the pulse input is gated according to the level input that existed during the interval before the pulse. The output is at the top, the delayed level input is at the bottom, and the differentiating level change or pulse input is on the side. The input signal to be differentiated, whether a level change or a pulse, is indicated by an arrowhead, rather than a diamond. The pulse symbols are hollow when positive-going and solid when nega- tive-going.
In the DCD gate, the pulse input must be positive-going. Since many DCD gates may be driven by the same pulse, the side of the rectangle opposite the pulse may be used to show a continuation of the same line, as in Figure 8. The illustration on the left below is a simplified version of the identical logical configuration on the right. It has two stable states representing and 1, and remains in one of these states until an appropriate command to change state is received.
Three commands may be given: set, which puts the flip-flop in the 1 state; clear, which puts the flip-flop in the state; and complement, which changes the state of the flip-flop regardless of its previous state. The flip-flop consists of two diode gates, connected "back-to-back. This holds transistor Q2 on, which in turn maintains the off condition of transistor Ql. Direct set and direct clear inputs are provided for operation of the flip-flops directly from external logical elements. When the flip-flop is set to the 1 state, the 1 output is at — 3v.
The gates provide sufficient delay so that information may be read out of one flip-flop and into another at the same time that the first flip-flop receives a command to change state. That is, both the pulse and level inputs of the DCD gate must meet the proper input requirements for an output signal to occur. Thus, a set signal will reach the flip-flop only if the flip-flop was previously in the state. Similarly, a clear command reaches a flip-flop only if it was previously in the 1 state.
For simplicity, this conditioning is not shown on the symbol but should be remembered because it is a very powerful element of the flip-flop. The gate inputs are still available for external enables. As illustrated in Figure 12, when the output of either diode gate Di or D 2 is asserted at ground , the corresponding flip-flop is cleared put to 0. If the gates are attached to the flip-flop through diode networks Figure 12a , the diode gate outputs D x and D 2 can be logically independent. If they are attached in parallel without diode networks Figure 12b , the ouputs will be dependent.
That is, if any output is at ground, the output of all gates connected in parallel with it will be at ground. The input to the delay, like that of the flip-flop, is through a DCD gate see Figure When the gate is properly enabled, and when its pulse input terminal is brought to ground by a positive pulse or a positive-going level change, the output of the delay changes from its normal ground level to a — 3v level for a fixed, but adjustable, period of time. After the fixed time has elapsed, the output returns to ground. This delayed output is suitable for driving many R series modules. A pulse output can be obtained with the addition of a pulse amplifier to the delay output.
Figure 13 Delay One-Shot Delay units are particularly useful in generating delayed pulses or signals of arbitrary width. The network of delays in Figure 14a will produce the waveform shown in Figure 14b. For example, when the same gating is to be done on an entire register of flip-flops, it is most economically performed at the input to the pulse amplifier which drives the register.
Figure 15 Pulse Amplifier with Gates Several pulse amplifier outputs may be ORed together by simply connecting their outputs in parallel Figure Thus two levels of logic can be performed by pulse amplifiers. This connection may be made directly or through the diode networks, as with the diode gates shown in Figure These clocks are often used as a primary source of timing for large systems Figure Figure 18 Clock Where precise timing is required, a clock with a single frequency crystal oscillator may be used.
The R series loading rules are simple because all inputs draw current from the same direction and because all inputs are either diode gate circuits or DCD circuits. Each diode gate input draws 1 ma milliampere and the output drives 20 ma. The load resistor draws 2 ma; so a diode gate with a clamped load resistor tied to it can drive 18 ma. A flip-flop is two slightly modified diode gates cross-connected. The direct set and clear terminals draw 1 ma. The output will drive 21 ma less 3 ma for the load resistor permanently connected in the flip-flop and less 1 ma for conditioning the opposite side of the flip-flop for a remainder of 17 ma.
It will drive 20 -2 or 18 ma. The pulse amplifiers will drive loads of up to 70 ma. The DCD gates on flip-flops, delays, and pulse amplifiers draw 2 ma at the level inputs and 3 ma at the pulse inputs. When two DCD gates are driving both sides of the same flip-flop, the load on both pulse inputs totals only 4 ma. When the level inputs are tied together as in a complement configuration, the total input load is only 3 ma, as shown in Figure Figure 19 Flip-Flop Input Loads On flip-flops which have built-in DCD gates, the output driving ability is less because the internal diode capacitor gate draws current from the flip-flop.
Table 2 lists the output driving capability for each of the six types of flip-flops. Examples follow of how some of these circuits are built using R series modules. When a flip-flop changes from the 1 to the state, its 1 output complements the next flip-flop in the counting chain. Flip- flop C, the first in the chain, complements on each input pulse. Flip-flop B complements when C changes from 1 to 0, and so on through the counter. Note that a flip-flop complements only if all preceding flip-flops are in the 1 state when the next input pulse arrives. The time required for a "carry" to propagate up the chain is 70 nsec per stage.
The input load for the complete circuit is only that required to complement flip-flop C. This input requires a nsec pulse, — 3v to ground, rather than a standard, nsec pulse or a level that remains at ground for more than nsec. This time is needed to hold all flip-flops in the state while the carries die out. Binary Down-Counter The binary down-counter is identical to the binary up-counter, except that the comple- menting level change comes from the terminal of the preceding flip-flop rather than the 1 terminal.
In the down-counter the direct set rather than the direct clear requires nsec pulses. The counting sequence is the reverse of the up counter, that is , ,. Binary Up-Down Counter The binary up-down counter is a combination of the up counter and the down counter. All pulse inputs are standard positive pulses, — 3v to ground. Both direct set and direct clear require nsec pulses. In order to avoid counting in both directions simultaneously, the DCD gate level inputs must be used. The two control lines must not be grounded simultaneously. Input pulses must not follow control line changes sooner than nsec to allow for DCD gate set up time.
Control line changes must not follow input pulses closer than 70 M-1 nsec, to allow an M bit counter time for carry propagation. Count sequency is shown in Table 3, and an example of a four-bit binary up-down counter is illustrated in Figure OOOO If N is an integral power of 2, the output is automatically produced by the final digit of a counter of the appropriate length.
If N is not a power of 2, gating must be performed to detect the desired number, produce a signal, and reset the counter to 0. Diode gates may be used to sense the number N-l, gate off the input to the counter, and reroute the Nth input. This method may be used for any value of N Figure Figure 23 illustrates how a count-of-5 counter is implemented. The input of flip-flop A is connected directly to the counter input rather than the output of flip-flop B.
Thus the last flip-flop is cleared on the first pulse after it has been set; that is, the states of the last flip-flop will be The level inputs of flip-flop C are connected to the 1 output of flip-flop A. This prevents the counter from counting when flip-flop A is in the 1 state has been set on. This counting sequence can easily be extended by adding several binary stages in place of flip-flop B. The 2''th pulse which sets the last flip-flop clears all previous flip-flops see "Binary Up Counters".
This BCD counter may be used wherever decimal results are desired. Longer duration decimal counters are made by using many BCD counters in series. With no additional gating, the R accepts inputs from five external sources, the R from two sources, the R from one source, and the R from two sources. Figure 25 illustrates a simple buffer register.
To correctly read in a number, the register is first cleared. Then each flip-flop is set in accordance with the state of the level input to its DCD gate. This operation can also be performed by setting all flip-flops and then reading in through clear gates. If any flip-flop is in the 1 state, its output is at ground enabling the 1 input of the next flip-flop. Hence the application of a shift pulse puts the second flip-flop into the 1 state. Similarly, a shift pulse puts.
At the time of the shift pulse, flip-ftop C is cleared if the read -in level has been at ground. If the read- in level has been at — 3v, flip-flop C is set to 1. Thus on each count pulse shift pulse the ring counter will shift the contents of the last flip-flop to the first flip-flop Table 4.
Switch-Tail Ring Counter A switch-tail ring counter can be made from a shift register by connecting the 1 output of the last flip-flop to the 1 level input of the first flip-flop and the output of the last flip-flop to the level input of the first. On each count pulse shift pulse , the switch- tail ring counter will shift the inverse of the contents of the last flip-flop into the first flip-flop Table 4.
A number is also read into flip-flops A, B, and C at the same time as the shift operation. When any of the three level inputs are at — 3v, a 1 is read into the cor- responding flip-flop. A is read in if the corresponding terminal is at ground. The augend is called the resident number and is stored in the accumulator register.
The addend, or incident number, is stored in the incident register. The sum appears in the accumulator. R series Type R, flip-flops can be used as shown in Figure The first step is a half-add. Each digit of the accumulator is complemented if the corresponding digit of the incident number is 1.
The second step is a carry. A carry is generated if a digit in the accumulator is and the corresponding incident number is 1. A carry is also propagated if an accumulator digit is 1 and it receives a carry pulse from the next less significant accumulator digit. Each stage will propagate one carry at most. After all carries have been propagated, addition is complete and the accumulator contains the sum of the incident and resident numbers.
Carry initiate must lag half add no less than nsec to allow sufficient set up time. Next half add must lag carry initiate by at least 50M nsec where M is word length in bits to allow for M bits of carry propagation. This pulse may be discarded, added to the first stage by means of the end-around-carry , or stored externally by means of an additional flip-flop. Three examples are shown in Table 5. To subtract a number from the accumulator, the number is made negative and added to the accumulator.
The steps involved in performing a subtraction depend on whether the l's complement or the 2's complement number system is used to represent a negative number. The l's complement number system is easiest to implement. To subtract a number from the accumulator, the steps are 1 complement the incident number, 2 half-add, and 3 carry. With this number system it is necessary to use the end-around-carry shown in Figure One's complement subtraction may also be performed by 1 comple- menting the accumulator, 2 half-add, 3 carry, and 4 recomplementing the accumu- lator.
Serial Adder Figure 29 illustrates a serial adder. The contents of register A are added to register B, and the sum is stored in register B. The two numbers to be added are read into registers A and B with the least significant bits stored in flip-flops AN and BN. The carry flip-flop may be cleared before addition is begun. When a shift pulse is received, the number in each flip-flop is advanced one place.
The least significant bits are added, together. If there is a carry, it is stored in the carry flip-flop. The most significant, or overflow, bit is stored in flip-flop C. This type of comparator Figure 30 has a multiple-input diode gate with each diode connected through a toggle switch to a flip-flop. Each toggle switch corresponds to a single bit; a closed switch represents a 1, an open switch represents a 0. In Figure 30, the counter goes from the binary number to the number , then resets to Note that with the single-throw toggle switches, number could also generate an out- put.
However, this number is never reached because the counter is reset after Since this action requires an additional input pulse to operate the pulse amplifier, the toggle switches must be adjusted to detect one less than the number of pulses to be counted, or the counter's least significant bit must be set while the rest of the counter is cleared. Table 6 shows the resulting counting sequences for each method. The diode gates are connected to the flip-flops so that a closed switch corresponds to a 0.
The first comparator output is used to preset the counter to the all 1 state, or to turn off the counter input. Comparing a toggle-switch register with a flip-flop register that does not necessarily start at requires a single-pole, double-throw switch for each bit. One side of a switch is connected to the 1 output of a flip-flop, and the other side, to the output. The rotor of the switch is connected to an input of the diode gate. When the state of any bit is to be detected, the toggle switch is connected to the terminal of that bit. Similarly, when the 1 state is to be detected, the toggle switch is connected to the 1 terminal of that bit.
Thus, the diode gate detects the desired register state regardless of the regis- ter's Counting sequence. Because of the carry propagation time through the counter, the maximum input frequency depends on the number of bits. For M bits, the maximum frequency is mc 70 M - - This allows nsec to enable the DCD gate and nsec delay through the diode gate and inverter. Comparing Two Flip-Flop Registers Comparison of two flip-flop registers, A and B, requires an exclusive OR for each corre- sponding pair of bits since two possible conditions produce an inequality: bit Al equals and bit Bl equals 1; or Al equals 1 and Bl equals 0.
The entire set of exclusive ORs must be ORed together to determine when any pair of bits is unequal. Figure 31 illus- trates the use of the Type R Diode Gate for comparison of two 3-bit registers. When the two registers are equal, the output is negative; when the two registers are unequal, the output is ground. Sign Of An Inequality A more sophisticated comparator is used to compare the numerical value of two registers to determine equality or the sign of an inequality.. Pairs of bits must be investi- gated in the order of their significance. Once an inequality has been discovered, all further investigation is stopped so that the differences in bits of lesser significance do not affect the output.
To begin investigation, the equality line is brought to — 3v. If there is equality, the negative signal is propagated down the equality line. If all corresponding pairs of both registers are equal, the negative signal appears at the end of the final stage. However, if an inequality is reached, further in- vestigation is stopped and the equality line output remains at ground.
If this inequality is such that register A is greater than register B, a ground signal is generated at the sign output. Asynchronous signals are often commands such as start, stop, or clear. Incompatible signals must be guarded against whenever a single flip-flop register is connected for more than one possible mode of operation. Synchronization is required in -a. Care must be taken that a split or partial pulse is not allowed to enter the system, because it could result in a partial shift, partial read- in, or partial read-out.
Likewise, a bidirectional shift register should never be commanded to shift left and shift right at the same time. In a bidirectional counter, particular care must be taken to assure that the add and subtract inputs are not pulsed simultaneously. A synchronizer is built by ANDing a random input signal and a clock or other primary pulse train and using the results of this AND gate to set a single flip-flop. If the random signal partially enables the pulse gate of the synchronizer flip-flop, the single synchronizer flip-flop decides whether the signal will be accepted or rejected. Provision must also be made for the rejected signal to be accepted by the next clock pulse; thus, the input signal may be slightly delayed by the synchronizer flip-flop, but there will be no middle state to activate only a portion of the main circuit.
When the input level is ground, the clock is gated through terminal A. When the input level is negative, the clock is gated through terminal B. If the input level has changed too recently to allow the DCD gates to fully set up before the clock pulse occurs, the decision to accept or reject the signal change is made by the syn- chronizer flip-flop only.
Thus, no pulses are gated through both terminals A and B at the same time, and no split pulses are gated through either terminal. This method, or a variation, is often used in controlling the direction of count in an up-down counter. The random start and stop pulses are converted to stop or start levels by flip-flop A. Flip-flop B converts this randomly changing level into a level that changes synchronously with the clock.
This level, in turn, conditions the output pulses. The action may be de- layed by one clock pulse; however, a split pulse will not be allowed to enter the main system. The operation of the synchronizer is similar to that shown in Figure 34 except that the stop command is automatically generated by the first pulse to leave the synchronizer.
Thus, only one pulse passes into the main system, and this pulse is synchronized with the clock. They can also make it possible to OR into an R-Series flip-flop output terminal for setting or clearing from several sources. Diode networks cannot be cascaded to perform other logic operations.
Propagation delay of R-Series gates expanded by R or R diodes will increase typically nsec when gate output rises from — 3v to Ov, but will not change noticeably when gate output falls from Ov to — 3v. Diodes used are similar to type IN Six of the circuits are used for single-input inversion; the seventh circuit can be used for gating by tying additional diode input networks to its node terminal. Clamped load resistors of 2 ma are a permanent part of each in- verter. Input load is 1 ma, shared among the inputs that are at ground. The combined length of all leads attached to the node terminal must not exceed 6 in.
Input signal and load characteristics for diode networks are the same as those given for the diode input above. Each inverter can drive 18 ma of load at ground. Output terminals of inverters may be connected in parallel. Some typical propagation delays are shown below. High frequency logic designs may benefit from the application note "Estimating Propagation Delays. Each gate has three input terminals: two are con- nected to diodes, a third is connected directly to the node point of the diode gate.
The third terminal allows the number of input diodes to be increased by adding external diode networks such as the R or R External diodes must be connected in the same direction as the diodes in the Rill. Unused inputs may be left open.
Node Terminal — Accepts only R or R net- works or their equivalent. The combined length of all leads attached to the node, terminal must not be greater than 6 in. Input signal and load character- istics for the diode networks are the same as those given for the diode above. Each output can drive 20 ma of load at ground.
Clamped load resistors are included in the module. Each clamped load resistor represents 2 ma of load. The output terminals of diode gates may be connected in parallel. Two gates in parallel driven by the same" signal can drive 38 ma at ground 20 ma each, less the 2-ma clamped load. If they are not driven by the same signal, gates in parallel drive 20 ma at ground minus 2 ma for each clamped load used. High frequency logic designs may benefit from the appli- cation note "Estimating Propagation Delays.
Input load is 1 ma, shared among the inputs at ground. Each output can drive 18 ma of load at ground. Output terminals may be connected in parallel.
Logic Designer's Handbook Circuits and Systems
Clamped loads included in the module are 2 ma each. High frequency logic designs may benefit from the applica- tion note "Estimating Propagation Delays. B 23 ma. This mod- ule increases density at the expense of flexibility, since gate expanders R and R cannot be used.
Input load is 1 ma,shared among the inputs that are at ground. Each output has a permanently attached 2 ma clamped load resistor. Delays are similar to Rill delays. See application note "Estimating Propagation Delay" for more information. Mini- mum duration: nsec at ground, nsec at — 3v. Input load is 1 ma at each input. Propagation delays for output rise are similar to Rill delays. Propagation delays for out- put fall, are typically 75 nsec longer than Rill delays. Clamped loads are not provided on this module, and must be obtained from some module in the asso- ciated logic.
Each of the six gates is a 1 ma load shared among its grounded inputs; thus inputs F, M, and T may be loaded with up to 2 ma at ground. Each output can drive up to 20 ma at ground. A 2 ma or heavier clamped load must be used at each group of paralleled collector outputs, chosen to provide fall times fast enough for the use intended. See application note "Estimating Propagation Delay" for more informa- tion. The output of each circuit is negative if its inputs are the same, and ground if they are different. If the outputs of several circuits are tied together, the common output line will be negative if every input pair matches, ground if any pair doesn't match.
During the transition from one input pattern to another with the same output, there is an interval during which the R output may be wrong for both patterns. Transitions between unequal inputs have a relatively short settling time, but transitions between equal inputs may produce transients to ground lasting nsec or more. Each input is a 2 ma load at ground. Each output can drive 18 ma at ground. Propagation delay for output rise is similar to Rill delay.
Propa- gation delay for output fall is typically nsec longer than Rill delay. The module contains a multiple-input diode gate with a transistor inverter for signal amplifica- tion. This module is frequently used to mix multiple inputs to a pulse amplifier, or to compare the contents of two flip-flop registers.
The back-to-back diode circuits are possible because of an internal bias resistor connected to the input of each second stage diode. The bias holds the input of the second stage at — 3v unless one of the first stage inputs is grounded. Propagation delay for out- put rise is similar to Rill delay. For output fall, delay is typically nsec longer than Rill delay under similar loading conditions, assuring sufficient pulse stretching to allow 70 nsec inputs. Output is typically too wide, however, to allow 2 mc rates.
Maximum rate depends upon R loading, and may be as low as 1 mc. In- put load is 1 ma per input pair shared by the grounded inputs. When any pair of inputs is not being used, at least one of the two must be grounded. The output can drive 20 ma of external load at ground. It has no internal load. When the enable input is at ground, the selected output line is at ground and the other seven outputs are at — 3v. When the enable input is at — 3v, all outputs are at — 3v. The internal gates are similar to those in the Rill. The enable input is the common emitter connection of the out- put inverters.
Typical total transition times are 75 nsec for output rise and 60 nsec for output fall. Input load is 2. The input current is 4 ma at ground when only one input is grounded, as in the last 6 lines of the truth table. Enable — Standard levels of — 3v and ground, nsec minimum duration. Input load at ground is 3 ma plus the current required by the load on the selected output when the inputs are binary, as in the first 8 lines of the truth table. For other inputs, the load is 3 ma per selected output plus the loads on those selected outputs. The maximum input current is 10 ma when driven from an inverter collector.
No more than one inverter can be placed in series with this pin and ground. If any external circuit brings an R output to ground, any gate being used to enable pin D must not drive anything else. Each octal output has a permanently attached 2-ma clamped load resistor. Each output can drive 7 ma of load at ground. If the enable input is permanently grounded, each output can drive 18 ma of load at ground.
The length of the wire used to ground the enable input pin D should be kept as short as possible. Note: Simultaneous switching of R outputs is not assured. If adjacent R outputs are ORed together for example, the gate output may contain spikes.
A 2-mc counter of any size, with all flip-flops switching simultaneously, can be constructed using the dc carry modules interconnected as in Figures 1 and 2 on the next page. The pulse amplifier interconnec- tion of Figure 1 should be used between the first pair of dc carry modules. The dc carry interconnec- tion of Figure 2 may be used between all following pairs of stages. The carry module contains an independent 1-input diode gate and six interconnected diode gates with two, three, four, five, six, and seven inputs respec- tively. The outputs are all similar to the Type R The input loads on Pins M and H are 6 ma each.
The loads presented by Pins D and L are 1 ma each. All loads are at ground, there is no load at -3v. Each output circuit can supply 18 ma at ground and has an internal load of 2 ma. It can be set and cleared at any frequency up to 2 mc. A set input makes the 1 output go to — 3v and the output to ground; a clear input makes the output go to — 3v and the 1 output to ground. INPUT: Direct Set and Clear — A standard nsec pulse or a ground level of nsec minimum dura- tion activates the input; the load at ground is 1 ma.
When not in use, the direct set and clear terminals must be at — 3v. If both inputs are held at ground, both outputs are at — 3v. Collector Triggering — The flip-flop can also be set or cleared through its output by a diode gate or a diode network. The triggering circuit load is the external load on the output termi- nal being driven plus the internal load. Each output can drive 17 ma of external load at ground. The internal load is 4 ma. If more than 18 in. The load is sufficient if the positive transi- tion at the opposite terminal reaches — lv within 80 nsec after the flip-flop is pulsed.
Note: Additional driving capability at —3 v is re- quired by some circuits outside the R series. Auxil- iary clamped loads W and W are available for this purpose. Because of this large number of inputs, the R can be used in any of the following applications without addi- tional gating: 1. Any two of the following as well as conditional read-in from an external source: up counter, shift register, jam transfer buffer, ring counter, and switch tail ring counter.
Down counters or up-down counters can also be implemented if conditional read-in is not required 2. BCD counter with read-in from two sources. Buffer register or control flip-flop with readin from five sources. If both inputs are held at ground, both outputs will be at— 3v. If the flip-flop is used in an up counter with carry gates enabled, the direct clear pulse must be at least nsec long to sup- press carry propagation. Similarly, if the down counter gates are enabled, the direct set pulse must be nsec long. Because DCD gates are internally conditioned by the state of the flip-flop, complement inputs may be formed by tying 1 and DCD gate inputs together.
A DCD gate is enabled by a ground level and disabled by a — 3v level. The con- ditioning level must be present for at least nsec before the gate is pulsed. The level input represents 2 ma of load at ground. When 1 and DCD gates are connected in parallel to form a complement input, the total level load is 3 ma at ground. Pulse — Standard nsec pulses — 3v to ground at any frequency up to 2 mc. It can also be driven by positive-going level changes — 3v to ground with rise times of 60 nsec max and duration of nsec min.
Prior to operation the input must have been at — 3v for at least nsec. The pulse input repre- sents 3 ma of load at ground. When a pair of 1 and DCD gates have a common pulse input, as in com- plementing or shifting, the total pulse load is 4 ma at ground. Collector Triggering — The flip-flop can also be set or cleared from its outputs by a diode gate circuit or a diode network.
The triggering circuit load is the external load on the terminal being driven by the circuit plus the internal load on that terminal. The carry propagate time is 70 nsec. The terminal can drive 11 ma of external load at ground. The internal load is 10 ma. The 1 terminal can drive 13 ma of external load at ground. The internal load is 8 ma. The load is sufficient if the positive transition at the opposite terminal reaches — lv within 80 nsec after the flip-flop is pulsed. Note: Additional driving capability at — 3v is re- quired by some circuits outside the R series.
Each has a direct clear input, a common set input, and two DCD gates. The R can perform in any one of the following applications without addi- tional gating: up counter, down counter, shift regis- ter, ring counter, jam transfer buffer, and switch tail ring counter. INPUT: Direct Set and Clear — A standard nsec pulse or a ground level of nsec minimum dura- tion activates the input; the load at ground is 1 ma for each clear input, and 2 ma for the set input. When not in use, the direct terminals must be at — 3v.
If the flip-flop is in an up counter with carry gates enabled, direct clear puJses must be at least nsec long to suppress carry propagation. In like manner, a ns set pulse must be used when the flip-flops are arranged as a down counter. Because DCD gates are internally con- ditioned by the state of the flip-flop, a complement input may be formed by tying the 1 and DCD gate inputs together. The conditioning level must be present for at least nsec before the gate is pulsed. When a pair of 1 and DCD gates have a common pulse input, as in complementing or shifting, the total pulse load is 4 ma at ground.
Collector Triggering — The flip-flop can also be set or cleared through its outputs by a diode gate circuit or a diode network. The triggering circuit load is the external load on the terminal being driven by the circuit plus the internal load on that terminal 6 ma each. Each terminal can drive 15 ma of exter- nal load at ground and has an internal load of 6 ma. The load is sufficient if the positive transition at the opposite terminal reaches — 1 v within 80 nsec after the flip-flop is pulsed. Each flip-flop has a direct clear input and a DCD gate for conditional read-in.
INPUT: Direct Clear — A standard nsec pulse or a ground level of nsec minimum duration activates the input; the load at ground is 1 ma. When not in use, the direct clear terminal must be at — 3v. The flip-flop can also be driven by positive-going level changes — 3v to ground with rise times of 60 nsec max and duration of nsec min. The pulse input represents 3 ma of load at ground. Collector Triggering — The flip-flop may also be set or cleared from its outputs by a diode gate circuit or a diode network.
The terminal can drive 15 ma of external load at ground. The internal load is 6 ma. The 1 terminal can drive 17 ma of external load at ground. Each has direct set and direct clear inputs. Two of the flip-flops share a common direct clear input. The R is used in general control applica- tions. A set input makes the 1 output — 3v and the output ground; a clear input makes the output — 3v and the 1 output ground. INPUT: Direct Set and Clear — A standard nsec pulse or a ground level of nsec minimum dura- tion activates the input; the load at ground is 1 ma per flip-flop.
If both inputs are held at ground, both outputs will be at — 3v. Collector Trig- gering—The flip-flop can also be set or cleared through its outputs by a diode gate circuit or a diode network. The internal load is 4 ma for each terminal. Each terminal can drive 17 ma of external load at ground, and has an internal load of 4 ma.
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Each has three DCD gates, and can be collector-triggered at either output by a diode-transistor gate or a diode network. The R can be used in any of the following applica- tions without additional gating: up counter, down counter, shift register, ring counter, or jam transfer register.
INPUT: Direct Clear — A standard nsec pulse or a ground level of nsec minimum duration acti- vates the input; the load at ground is 1 ma. If the flip-flop is used in an up counter with carry gates enabled, direct clear pulses must be at least nsec long to suppress carry propagation. The conditioning level must be present for at least ' nsec before the gate is pulsed. When 1 and DCD gates are connected in parallel to form a complement input, the total load is 3 ma at ground. Prior to opera- tion the input must have been at — 3v for at least nsec.
When a pair of 1 and DCD gates have a common pulse input as in complementing or shift- ing, the total pulse load is 4 ma at ground. Collector Triggering — Triggering circuit load is the external load on the terminal being driven plus the internal load on that terminal. Internal load for the 1 termi- nal is 6 ma; for the terminal, 8 ma. Carry propagation time is 70 nsec.
The terminal can drive a ma external load at ground; the 1 terminal, 15 ma at ground. Internal load on the 1 terminal is 6 ma; for the terminal, 8 ma. The length of the delay is determined by the capacitor and potentiometer. External potentiometers can be attached between terminals J and L S and U. The total resistance between these terminals must not exceed 20 kilohm.
Delay jitter due to power supply ripple is less thar. The total capacitance, C, equals pf of in- "ternal capacitance plus any external capacitance used. The resistance, R, is equal to the resistance of the potentiometer plus 1 kilohm of internal re- sistance. The minimum delay is nsec. The min- imum delay in nsec for a given external capacitor is C where C is equal to the external capacitance in pf plus a pf internal capacitance. The re- covery time is twice the minimum delay. For best results, use wet-slug tantalum electrolytics for delays of several seconds or more.
Four volt ratings are adequate in most cases, but 6 or 8 volt ratings may be desirable to further reduce leakage in some cases. Remote Control Wiring: Noise picked up on wires leading to remote timing capacitors' or rheostats tends to synchronize the end of the delay period or it could cause false triggering in extreme cases. Even for 1 ft control wires, a grounded shield may be advisable if smooth control and freedom from jitter are essential.
A DCD gate is enabled by ground level and disabled by a — 3v level. Pulse — Standard nsec pulses — 3v to ground. The delay cannot be set from its out- put terminal. The output can drive 18 ma of ex- ternal load at ground. The internal load is 2 ma. Its unusual characteristics include the ability to respond to in- puts even while in the ONE state, so that successive inputs above a preset frequency can postpone the return to ZERO indefinitely. This characteristic can be used, for example, to detect gaps in an otherwise continuous pulse train, or to determine whether an input pulse rate is above or below a preset fre- quency threshold.
The module can also be used to establish initial conditions after system power is in- terrupted, since it always goes to the ONE state when the power' is first applied. Delay is 3. Jitter is less than 1. The load at ground is 1 ma. Extra 10 ma clamped loads may be connected to change the driving capability at each output to 8 ma at ground, 7 ma at — 3v. The ONE output will be at — 3v duri. The ZERO output is grounded'dur- ing the delay period and — 3v otherwise. Ranges are separated by approximately a factor of ten. For extra long delays, connect an external ca- pacitor from pin J to ground.
To use the internal rheostat, connect pin P to pin R. For external control, connect a variable resistance no larger than 20, ohms from pin P to pin S. Substantially the same R and C are required in the R as in the R for a given delay, taking into account the ten times larger minimum capacitance built into the R If elec- trolytic capacitors are used, at least a 6-volt rating is required. The variable, clock is often used as a primary source of timing for large systems.
The frequency of the R Clock is variable from 30 cps to 2.
Five capacitors provide coarse frequency control, and a built-in 20,ohm poten- tiometer permits fine adjustment. Terminals for an external potentiometer or capacitor are available. The maximum size of the external potentiometer to be used is 20, ohms. The pulse-to-pulse jitter is less than 0. The pulses that follow appear at the frequency selected. The clock may be disabled by applying a ground level at the enable gate pin S.
The enable gate loading is 4 ma at ground. Disable duration must exceed the period to which the clock is set. The output can drive 70 ma of external load at ground.